Is there a T-State timing table available?

Profile picture for user Mr.Blinky
Submitted by Mr.Blinky on Mon, 08/30/2021 - 19:31

I was just wondering if someone made a complete T-state timing table yet for all Z80 instructions with timings for Sam ROM / external RAM, and internal RAM with and without contention?

Profile picture for user Stefan Drissen
Stefan Drissen Tue, 08/31/2021 - 12:57

Since SimCoupe handles memory contention perfectly, you can find it all in the code :-)

See for example https://github.com/simonowen/simcoupe/commit/d3a99f0b36a710da85aa897fbea2cacaf0ff1cba

Profile picture for user Mr.Blinky
Mr.Blinky Tue, 08/31/2021 - 19:00

Thanks for replying David, I read the article in Based on an Idea. when I searched for T-States on WorldOfSam. Nice mag. The accelerator artivle looks like a interesting read too. But the Table isnt isn't complete.

Also thanks for repying Stefan. I'd thought I ask first if there is a convenient table before diving into the Sim Coupe source ;)

 

Profile picture for user Mr.Blinky
Mr.Blinky Thu, 09/02/2021 - 20:44

Oops. Don't know what went wrong but the reply I posted didn't got posted. Maybe subject is mandatory? Hope this one gets through.

 

Thank you all for the replies.

@David. First thing I did before posting was searching WorldOfSam and found Based on an Idea. Nice magazine. Will have to read it thourougly later. However The T-States  table there doesn't include the IO ports and contended timings.

@Stefan. I know. I just asked if there was a table before diving into sourcode. A table is so much more convenient ;)
 

Simon Owen Mon, 09/06/2021 - 17:22

I've got a program that can probably generate what you need, using the same CPU core and contention rules as SimCoupe. I started on something to use for SimCoupe unit testing, but there's no reason it couldn't generate a table instead.

There are actually quite a few combinations involved, but I suspect many are not be very useful. For example, the code can be running in ROM/IntRAM/ExtRAM, the data it's manipulating can be in ROM/IntRAM/ExtRAM, and the raster can be over Border/Screen during execution. Of the 18 possibilities I suspect the useful ones are:

- code in IntRAM, data in IntRAM, raster over Border
- code in IntRAM, data in IntRAM, raster over Screen
- code in ROM, data in IntRAM, raster in Border
- code in ROM, data in IntRAM, raster in Screen
- code in ExtRAM, data in IntRAM, raster over Border
- code in ExtRAM, data in IntRAM, raster over Screen
- code in ExtRAM, data in ExtRAM (no contention!)

So that would be 7 columns for each instruction group. Any others?

I've not included screen disabled or mode 1 as they're covered above. When the screen is disabled it's treated as Border (4T access rounding). The extra mode 1 contention stripes are treated as Screen (8T access rounding). You're on your own with instructions that span boundaries, though the SimCoupe debugger will help you there (and with timing in general).

I/O is contended for ports 0xf8 and above, but I'll include contended/uncontended figures in I/O instructions.

I'll ping you when I've got something to try, and once settled I can link it here.

Profile picture for user Mr.Blinky
Mr.Blinky Mon, 09/06/2021 - 18:52

Hi Simon!

Thanks for the reply.

Yes I'm looking for a table like that. Although the ROM and ExtRAM can be in the same column as they have identical timings, right?

 

 

 

Simon Owen Mon, 09/06/2021 - 20:23

You make a very good point! That's maybe just 5 columns then...

Simon Owen Tue, 09/07/2021 - 17:41

Hopefully this should be pretty close: https://simonowen.com/sam/timings/

I've checked most of the Ext/Ext cases, which should match the official Z80 timings. Other values look reasonable, but I'd like to check some in more detail to be sure. If you suspect errors please let me know!

Profile picture for user Mr.Blinky
Mr.Blinky Tue, 09/07/2021 - 19:27

Thanks Simon for the detailed info and the timing table. They will be of good use.

One thing is for sure: I'm gonna build a 1Meg ramdrive + extras :D

Profile picture for user Mr.Blinky
Mr.Blinky Sat, 09/11/2021 - 21:53

Ooo nice! Thanks for adding it to World of SAM. I see he also chose to use those 512K SRAMs and theres space for a EDDAC too :D Ahhh.. Seeing this wan't me work work on mycrazy but not so crazy 1MEG  idea.

Back on T-states. I found my little T-state counter interface again and did some fun testing with it. Sometimes read and writes to asic ports don't get that extra delay depending if there is a multiple of 4 or 8 Tstates between them. Just as as Simon wrote on his Timing page ' I/O accesses to ASIC ports are always limited to 1 cycle in every 8. '

in a,(&F8)
in a,(&F8)

Takes the same 32 Tstates as:

nop
in a,(&F8)
nop
in a,(&F8)

and found out that doing a bunch of INI/OUTI  or using just a INIR/OTIR takes the same amount of T-states when accessing an ASIC port 😂

 

 

Profile picture for user Dan Dooré
Dan Dooré Sat, 09/11/2021 - 23:29

Can you add a quick page for the T-state counter interface on WoSAM please!

Profile picture for user Dan Dooré
Dan Dooré Mon, 09/13/2021 - 08:58

Nice one! Always good to have the technical content up here :-)

Profile picture for user Stefan Drissen
Stefan Drissen Sun, 10/03/2021 - 15:11

I was revisiting timing in the mod player and noticed that there are two combinations I need missing:

  • code in IntRAM, data in ExtRAM, Border
  • code in IntRAM, data in ExtRAM, Screen

Could they be added?

Thanks!